1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device including memory cells connected to a ground line. The present invention has particular applicability to a static random access memory (SRAM).
2. Description of the Background Art
In recent years, static random access memories (hereinafter referred to as "SRAMs") using thin film transistors (hereinafter referred to as "TFTs") have been developed and marketed to meet the requirements for higher degree of integration and low power consumption of semiconductor memory devices. An example of the SRAM using TFTs is disclosed in a paper entitled "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs" (1990, International Electron Devices Meeting (IEDM), pp 469-472).
Although the invention can be generally applied to the semiconductor memories including memory cells connected to a ground line, an example in which the present invention is applied to the SRAM will be described hereinafter.
FIG. 13 is a block diagram of a conventional SRAM. Referring to FIG. 13, an SRAM 100 includes a memory cell array 1, an X decoder 2, a Y decoder 3, a sense amplifier 5, an output buffer 6, an input buffer 7 and a write circuit 8.
Memory cell array 1 includes a large number of memory cells MC disposed in rows and columns. In FIG. 13, each of memory cell groups 1r, 1r, . . . , arranged in a lateral direction is a row, and each of memory cell groups 1c, 1c, . . . , arranged in a vertical direction is a column. X decoder 2 selects a row in memory cell array 1. Y decoder 3 selects a column in memory cell array 1. Sense amplifier 5 amplifies a data signal read out from the memory cell MC. Output buffer 6 provides the amplified data signal as output data DO. Input buffer 7 receives externally applied input data DI. Write circuit 8 amplifies an input data signal to write the resultant signal in a desired memory cell MC. In FIG. 13, a line 100 also indicates a semiconductor substrate.
In reading operation, the X-decoder 2 activates one of word lines WL in response to an externally applied X-address signal XA. A data signal, which is stored in the memory cell MC connected to the activated word line WL, appears on bit lines BLa and BLb. The Y-decoder 3 selects one bit line pair in response to an externally supplied Y-address signal YA. More specifically, one of switch circuits in a Y-gate circuit 4 is rendered conductive in response to an output signal supplied from the Y-decoder 3, and therefore the data signal on one bit line pair is applied to the sense amplifier 5. The applied data signal is amplified by the sense amplifier 5, and then is supplied as the output data DA through the output buffer 6.
In writing operation, input data DI is applied through the input buffer 7 to a write circuit 8. The applied data signal is amplified by the write circuit 8, and then is applied to the gate circuit 4. The Y-decoder 3 sets one of the switch circuits in the gate circuit 4 conductive in response to the Y-address signal YA, and therefore the amplified data signal is applied to the corresponding bit line pair. The X-decoder activates one of the word lines WL in response to the X-address signal XA, and therefore the input data DI is stored in the designated memory cell.
FIG. 14 is a circuit diagram using TFTs. Referring to FIG. 14, the memory cell MC includes PMOS transistors 105 and 106 and MMOS transistors 101 and 102, which form a data storing circuit, as well as NMOS transistors 103 and 104 serving as access gate transistors. The transistors 105 and 106 are formed of the TFTs described before. A source of the driver transistor 101 is connected to a ground line GL through a direct contact resistance R1, which will be described later. Likewise, a source of the driver transistor 102 is connected to a ground line GL through a direct contact resistance R2. The transistors 103 and 104 are connected at their gates to the word line WL.
In writing operation, the bit line (e.g., BLa) attains a high level and the bit line BLb attains a low level and thereafter the word line WL is activated. Since the transistors 103 and 104 are turned on, nodes N1 and N2 of the data storing circuit change to the high and low levels, respectively. In this data stored state, the transistors 102 and 105 are turned on, and the transistors 101 and 106 are turned off.
In reading operation, when the word line WL is activated, a current I flows from a power supply potential Vcc to a ground potential, as shown in FIG. 14. More specifically, the current I flows to the ground line GL through a bit line load transistor 111, access gate transistor 104 and driver transistor 102. In this current path I, there exists the direct contact resistance R2 and an interconnection resistance r, so that a potential of a ground node N4 of the memory cell MC is raised. Thus, during the activation of the word line WL, the current I flows through the memory cell MC toward the ground line GL, whereby the potential of ground node N4 rises.
This current I is referred to as a "column current". Since the column current I is a thousand to a million times as large as the currents flowing through the TFTs 105 and 106, the rise of the potentials of ground nodes N3 and N4 is a remarkable problem particularly in the SRAM.
FIG. 15 is a schematic block diagram of a memory cell array including the memory cells shown in FIG. 14. Referring to FIG. 15, the memory cell array includes memory cells M41'-M78' disposed in rows and columns. Word lines WL1-WL4 are connected to the memory cells in first to fourth rows. The memory cells M41'-M48' and M51'-M58' in the first and second rows are connected to a ground line GL1 through direct contact resistances R. Likewise, the memory cells M61'-M68' and M71'-M78' in the third and fourth rows are connected to the ground line GL2. Each of the ground lines GL1 and GL2 includes the interconnection resistance r. The ground lines GL1 and GL2 are connected to common ground lines GNDLa and GNDLb.
The word lines WL1-WL4 and ground lines GL1 and GL2 extending in a lateral direction in FIG. 15 are formed of polysilicon layers or polycide layers on the semiconductor substrate. Meanwhile, the ground lines GNDLa and GNDLb extending in a longitudinal direction in FIG. 15 are formed of aluminium interconnections. In general, the aluminium has a resistance lower than that of polysilicon and polycide. Therefore, the longitudinal ground lines GNDLa and GNDLb in FIG. 15 are made of aluminium for reducing the resistances of ground lines. Although not shown in FIG. 15, the bit lines are formed of longitudinal aluminium interconnections in FIG. 15.
FIG. 16 shows a layout of the memory cells M62' and M63' of FIG. 15 formed on the semiconductor substrate. In this layout, the transistors 101, 102, 103 and 104 shown in FIG. 14 among the transistors forming the memory cell M62' are depicted. The PMOS transistors 105 and 106 formed of TFTs do not appear in the layout diagram of FIG. 16.
Referring to FIG. 16, the memory cell M62' includes first polysilicon layers 214 and 215, which form the transistors 101 and 102, respectively, as well as first polysilicon layers 212' forming the transistors 103 and 104, respectively. Regions AR surrounded by dashed lines are active regions formed in the semiconductor substrate. A source of the transistor 101 is connected through a direct contact DC2 to the ground line (GL2) formed of a third polysilicon layer 230. Likewise, a source of the transistor 102 is connected through a direct contact DC1 to the third polysilicon layer 230. Other memory cells M52', M53' and M63' have layouts similar to those of the memory cell M62'.
FIG. 17 is a cross section of a structure including the direct contact DC2 shown in FIG. 16. Referring to FIG. 17, a P-type well 251 is formed on an N-type semiconductor substrate 250. Insulating layers 241 and 242 are formed on the P-type well 251. First polysilicon layers 215 and 216 are formed on the insulating layers 241 and 242, respectively. The first polysilicon layers 215 and 216 are insulated by an insulator 240. A third polysilicon layer (i.e., ground line GL2) 230 insulated by the insulator 240 is directly connected to an active region AR1 formed in the P-type well 251. At a contact portion between the third polysilicon layer 230 and active region AR1, there exists a resistance, which is referred to as a "direct contact resistance". The direct contact resistances R1 and R2 shown in FIG. 14 and the direct contact resistance R shown in FIG. 15 are caused in this manner, because the ground line is formed of polysilicon.
FIG. 18 is a circuit diagram showing the currents flowing through the ground line GNDLa in the memory cell array in FIG. 15. Referring to FIG. 18, upon activation of the word line WL1, column currents I1-I5 flow from the memory cells M41'-M45' to the ground line GL1, respectively. Each of the currents I1-I5 flows through the corresponding direct contact resistance R and interconnection resistance r to the ground lines GNDLa and GNDLb (=0 volt). As can be seen from FIG. 18, nearer to the end of the ground line GL1, in other words, nearer to the ground line GNDLa, the current flowing through the ground line GL1 increases. Since the ground line GL1 includes the interconnection resistance r, the potentials at respective positions on the ground line GL1 change dependent on the existence of the currents I1-I5.
Thus, as indicated by curve C2 in FIG. 19, the potential VGL1 changes the position by position on the ground line GL1. In particular, as the current flowing through the ground line GL1 increases, the potentials at respective positions on the ground line GL1 rise.
The rise of potentials of the ground line GL1 destroys the data stored in the memory cells. In particular, as can be seen from curve C2 in FIG. 19, the maximum rise of potential is caused at a central portion of the ground line GL1, so that data stored in the memory cells M44' and M45' at the central positions among the memory cells M41'-M48' is particularly liable to be destroyed.
In addition, there is another problem. Referring to FIG. 18 again, the column current supplied, e.g., from the memory cell M42' flows as a current I2 from the right side in the figure in some cases, and also flows as a current I2' from the left side in other cases. When the column current I2 flows from the memory cell M42', a potential VN14 of a common connection node N14 of the memory cells M41' and M42' is expressed by the following expression. EQU VN14=(I1+I2+I3+I4).multidot.2r+I1.multidot.R (1)
When the column current I2' flows from the memory cell M42', a potential VN14' of the node N14 is expressed by the following expression. EQU VN14'=(I1+I2+I3+I4).multidot.2r+(I1+I2').multidot.R (2)
For example, it is assumed that each of the column currents I1-I4 is 20 .mu.A, the direct contact resistance R is 500.OMEGA., and the interconnection resistance r is 20.OMEGA.. The potentials VN14 and VN14' in the respective cases are expressed by the following expressions. EQU VN14=1.6.times.10.sup.-2 +1.0.times.10.sup.-1 =0.116V (3) EQU VN14'=1.6.times.10.sup.-2 +2.0 .times.10.sup.-1 =0.216V (4)
As can be seen from the foregoing expressions (1)-(4), when the word line WL1 is activated, the potential of the connection node N14 changes, depending on a state of storage of data in the memory cell M42', which may also destroy data as described before. The changes of potentials VN14 and VN14' are represented by curves C3 and C4 in FIG. 20. In FIG. 20, the ordinate represents the potential, and the abscissa represents positions of nodes N13 and N14.